A power MOSFET is voltage controlled, but that does not mean the gate is electrically insignificant. The gate behaves like a nonlinear capacitive load that must be charged and discharged every switching cycle.
The speed and quality of this gate transition strongly influence switching loss, dv/dt, di/dt, ringing and EMI.
Gate charge is often more useful than input capacitance
Datasheets usually list input capacitance, Ciss, but total gate charge, Qg, is often more useful for driver design because it reflects the actual charge needed through the switching transition.
A first-order driver-power estimate is:
Pgate ≈ Qg × Vgate × fsw
The higher the gate charge and switching frequency, the more power the driver must move into and out of the gate.
The Miller plateau
During turn-on, the gate voltage rises until the MOSFET begins to conduct. Then a portion of the gate charge is used to change the drain-source voltage rather than increase gate voltage significantly.
This interval appears as the Miller plateau.
The plateau is important because it corresponds closely to the period in which drain voltage and current overlap, creating switching loss.
The driver's available current during this interval can therefore have a major influence on switching speed.
Driver current sets transition speed
A simplified relationship is:
Igate ≈ Q / t
If a certain amount of gate charge must be moved in a short time, the driver needs sufficient source or sink current.
A weak driver produces slower transitions. That can reduce ringing and EMI, but it also extends the time during which the MOSFET simultaneously supports voltage and current, increasing switching loss.
A very strong driver can reduce switching loss but may produce excessive dv/dt, di/dt, ringing or false turn-on elsewhere in the circuit.
The fastest possible transition is therefore not always the best transition.
Gate resistance is a tuning tool
An external gate resistor is commonly used to control transition speed. Increasing resistance generally slows the switching edge; reducing it speeds the edge.
Some designs use separate turn-on and turn-off resistors with a diode network because the optimum speed can differ in each direction.
Gate resistance can be tuned to balance:
- switching loss;
- voltage overshoot;
- current overshoot;
- EMI;
- driver stress;
- susceptibility to false turn-on.
Common-source inductance matters
The source connection used by the power current is not electrically ideal. Parasitic inductance in the source path creates a voltage proportional to L × di/dt.
This voltage effectively opposes the gate drive during fast current transitions and can slow or distort switching.
Packages with a Kelvin source pin separate the gate-driver return path from the main power-source path, reducing this feedback effect.
This can materially improve switching control in fast, high-current designs.
Beware of Miller-induced turn-on
In a half bridge, rapid movement of one switch node can capacitively couple through the opposing MOSFET's gate-drain capacitance. If the induced gate voltage rises above threshold, the supposedly off device may partially turn on.
Possible countermeasures include:
- stronger turn-off drive;
- lower gate-loop inductance;
- appropriate gate resistance;
- negative off-state gate bias in demanding designs;
- Miller clamp functions;
- careful device selection.
Layout is part of the gate driver
Even a good gate-driver IC can perform poorly if connected through a long, inductive loop.
Keep the gate-drive loop compact. Place the driver close to the MOSFET where practical, use a low-inductance return path and separate sensitive gate routing from noisy switching nodes.
The complete view
Gate-drive design is a controlled trade-off. Slower switching can reduce EMI but increase loss. Faster switching can improve efficiency but increase ringing and stress.
The objective is not maximum speed. It is the switching speed that gives the best overall electrical, thermal and EMC behaviour for the application.